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freescale semiconductor hardware specification document number: mcf5235ec rev. 2, 08/2006 contents ? freescale semiconductor, inc., 2006. all rights reserved. the mcf523 x is a family of highly-integrated 32-bit microcontrollers based on the v2 coldfire microarchitecture. featuri ng a 16 or 32 channel etpu, 64 kbytes of internal sram, a 2-bank sdram controller, four 32-bit timer s with dedicated dma, a 4 channel dma controller, up to 2 can modules, 3 uarts and a queued spi, the mcf523 x family has been designed for general purpose industrial control applications. it is also a high-performance upgrade for users of the mc68332. this document provides an overview of the mcf523 x microcontroller family, as well as detailed descripti ons of the mechanical and electrical characteristi cs of the devices. the mcf523 x family is based on the version 2 coldfire reduced instruction set computing (risc) microarchitecture operating at a core frequency of up to 150 mhz and bus frequency up to 75 mhz. 1 mcf523x family configurations . . . . . . . . . . . . . . . . . . . 2 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 design recommendations . . . . . . . . . . . . . . . . . . . . . . . 9 6 mechanicals/pinouts and part numbers . . . . . . . . . . . . 14 7 preliminary electrical characteristics . . . . . . . . . . . . . . 23 8 documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 document revision history . . . . . . . . . . . . . . . . . . . . . . 44 mcf523x integrated microprocessor hardware specification by: microcontroller division
mcf523x integrated microprocessor hardware specification, rev. 2 mcf523x family configurations freescale semiconductor 2 1 mcf523 x family configurations 2 block diagram the superset device in the mcf523 x family comes in a 256 mold array process ball grid array (mapbga) package. figure shows a top-level block diagram of the mcf5235, the superset device. table 1. mcf523 x family configurations module mcf5232 mcf5233 mcf5234 mcf5235 coldfire v2 core with emac (enhanced multiply-accumulate unit) xxxx enhanced time processor unit with memory (etpu) 16-ch 6k 32-ch 6k 16-ch 6k 32-ch 6k system clock up to 150 mhz performance (dhrystone/2.1 mips) up to 144 instruction/data cache 8 kbytes static ram (sram) 64 kbytes interrupt controllers (intc) 2 2 2 2 edge port module (eport) x x x x external interface module (eim) x x x x 4-channel direct-memory access (dma) xxxx sdram controller x x x x fast ethernet controller (fec) ? ? x x cryptography - security module for data packets processing ??? x watchdog timer (wdt) x x x x four periodic interrupt timers (pit) x x x x 32-bit dma timers 4 4 4 4 qspi xxxx uart(s) 3333 i 2 cxxxx flexcan 2.0b - controller-area network communication module 1212 general purpose i/o module (gpio) xxxx jtag - ieee 1149.1 test access port xxxx package 160 qfp 196 mapbga 256 mapbga 256 mapbga 256 mapbga
features mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 3 mcf5235 block diagram 3features for a detailed feature list see th e mcf5235 reference manual (mcf5235rm). 64 kbytes sram (8kx16)x4 flexcan etpu eim ethernet v2 coldfire cpu intc0 watchdog pit0 jtag tap cache (1kx32)x2 pit1 pit2 pit3 4 ch dma uart 0 uart 1 i 2 c qspi dtim 0 dtim 1 dtim 2 dtim 3 timer padi ? pin muxing pll clkgen uart 2 8 kbytes edge port sdramc chip ebi selects (to/from padi) (to/from etpu cantx canrx fast controller (fec) fec dt n in dt n out u n rxd untxd i2c_sda i2c_scl sdramc qspi u n rts u n cts ports cim (to/from padi) nexus (gpio) d[31:0] a[23:0] r/ w cs [3:0] ta tsiz[1:0] tea bs [3:0] div emac dreq [2:0] intc1 arbiter (to/from sram backdoor) (to/from arbiter backdoor) skha rnga mdha (to/from padi) cryptography modules (x2) dack[2:0] bdm (to/from intc) mux padi) jtag_en
mcf523x integrated microprocessor hardware specification, rev. 2 signal descriptions freescale semiconductor 4 4 signal descriptions this section describes signals that connect off chip, including a tabl e of signal properties. for a more detailed discussion of the mcf523 x signals, consult the mcf5235 reference manual (mcf5235rm). 4.1 signal properties table 2 lists all of the signals grouped by function. the ?dir? column is the direction for the primary function of the pin. refer to section 6, ?mechanicals/pinouts and part numbers ,? for package diagrams. note in this table and throughout this docum ent a single signal within a group is designated without square brackets (i.e., a24), while designations for multiple signals within a group use brackets (i.e., a[ 23:21]) and is meant to include all signals within the two br acketed numbers when these numbers are separated by a colon. note the primary functionality of a pin is no t necessarily its default functionality. pins that are muxed with gpio will default to their gpio functionality. table 2. mcf523x signal information and muxing signal name gpio alternate 1 alternate 2 dir. 1 mcf5232 160 qfp mcf5232 196 mapbga mcf5233 256 mapbga mcf5234 256 mapbga mcf5235 256 mapbga reset reset ? ? ? i 83 n13 t15 t15 t15 rstout ? ? ? o 82 p13 t14 t14 t14 clock extal ? ? ? i 86 m14 p16 p16 p16 xtal ? ? ? o 85 n14 r16 r16 r16 clkout ? ? ? o 89 k14 m16 m16 m16 mode selection clkmod[1:0] ? ? ? i 19,20 g5, h5 j3, j2 j3, j2 j3, j2 rcon ? ? ? i 79 k10 p13 p13 p13 external memory interface and ports a[23:21] paddr[7:5] cs [6:4] ? o 126, 125, 124 b11, c11, d11 b14, c14, a15 b14, c14, a15 b14, c14, a15
signal descriptions mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 5 a[20:0] ? ? ? o 123:115, 112:106, 102:98 a12, b12, c12, a13, b13, b14, c13, c14, d12, d13, d14, e11, e12, e13, e14, f12, f13, f14, g11, g12, g13 b15, b16, c15, c16, d16, d15, d14, e16, e15, e14, e13, f15, f14, f13, g15, g14, g13, h16, h15, h14, h13 b15, b16, c15, c16, d16, d15, d14, e16, e15, e14, e13, f15, f14, f13, g15, g14, g13, h16, h15, h14, h13 b15, b16, c15, c16, d16, d15, d14, e16, e15, e14, e13, f15, f14, f13, g15, g14, g13, h16, h15, h14, h13 d[31:16] ? ? ? o 21:24, 26:30, 33:39 g1, g2, h1, h2, h3, h4, j1, j2, j3, j4, k1, k2, k3, k4, l1, l2 k4, k3, k2, k1, l4, l3, l2, l1, m3, m2, m1, n2, n1, p2, p1, r1 k4, k3, k2, k1, l4, l3, l2, l1, m3, m2, m1, n2, n1, p2, p1, r1 k4, k3, k2, k1, l4, l3, l2, l1, m3, m2, m1, n2, n1, p2, p1, r1 d[15:8] pdatah[7:0] ? ? o 42:49, m1, n1, m2, n2, p2, l3, m3, n3, r2, t2, n3, p3, r3, t3, n4, p4, r2, t2, n3, p3, r3, t3, n4, p4, r2, t2, n3, p3, r3, t3, n4, p4, d[7:0] pdatal[7:0] ? ? o 50:52, 56:60 p3, m4, n4, p4, l5, m5, n5, p5 r4, t4, p5, r5, n6, p6, r6, n7 r4, t4, p5, r5, n6, p6, r6, n7 r4, t4, p5, r5, n6, p6, r6, n7 bs [3:0] pbs[7:4] cas [3:0] ? o 143:140 b6, c6, d7, c7 c9, b9, a9, a10 c9, b9, a9, a10 c9, b9, a9, a10 oe pbusctl7 ? ? o 63 n6 t7 t7 t7 ta pbusctl6 ? ? i 97 h11 k14 k14 k14 tea pbusctl5 dreq1 ?i ? j14 k13 k13 k13 r/w pbusctl4 ? ? o 96 j13 l16 l16 l16 tsiz1 pbusctl3 dack1 ? o ?p6n8n8n8 tsiz0 pbusctl2 dack0 ? o ?p7p8p8p8 ts pbusctl1 dack2 ? o ? h13 k16 k16 k16 tip pbusctl0 dreq0 ? o ? h12 k15 k15 k15 chip selects cs [7:4] pcs[7:4] ? ? o ?b9, a10, c10, a11 c12, a13, c13, a14 c12, a13, c13, a14 c12, a13, c13, a14 cs [3:2] pcs[3:2] sd_cs[1:0] ? o 134,133 a9, c9 b12, d12 b12, d12 b12, d12 cs1 pcs1 ? ? o 130 b10 b13 b13 b13 cs0 ? ? ? o 129 d10 d13 d13 d13 sdram controller table 2. mcf523x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5232 160 qfp mcf5232 196 mapbga mcf5233 256 mapbga mcf5234 256 mapbga mcf5235 256 mapbga
mcf523x integrated microprocessor hardware specification, rev. 2 signal descriptions freescale semiconductor 6 sd_we psdram5 ? ? o 93 k13 l13 l13 l13 sd_scas psdram4 ? ? o 92 k12 m15 m15 m15 sd_sras psdram3 ? ? o 91 k11 m14 m14 m14 sd_cke psdram2 ? ? o ? e8 c10 c10 c10 sd_cs [1:0] psdram[1:0] ? ? o ? l12, l13 n15, m13 n15, m13 n15, m13 external interrupts port irq [7:3] pirq[7:3] ? ? i irq7=64 irq4=65 n7, m7, l7, p8, n8 r8, t8, n9, p9, r9 r8, t8, n9, p9, r9 r8, t8, n9, p9, r9 irq2 pirq2 dreq2 ? i ?m8t9t9t9 irq1 pirq1 ? ? i 66 l8 n10 n10 n10 etpu tpuch31 ? ecol ? ? ?f3 ?f3 tpuch30 ? ecrs ? ? ?f4 ?f4 tpuch29 ? erxclk ? ? ?e3 ?e3 tpuch28 ? erxdv ? ? ?e4 ?e4 tpuch[27:24] ? erxd[3:0] ? ? ? d3, d4, c3, c4 ? d3, d4, c3, c4 tpuch23 ? erxer ? ? ?d5 ?d5 tpuch22 ? etxclk ? ? ?c5 ?c5 tpuch21 ? etxen ? ? ?d6 ?d6 tpuch20 ? etxer ? ? ?c6 ?c6 tpuch[19:16] ? etxd[3:0] ? ? ? b6,b5, a5, b7 ? b6,b5, a5, b7 tpuch[15:0] ? ? ? 11, 10, 7:2, 159:154, 152, 151 e2, e1, d1 d2, d3, c1, c2, b1, b2, a2, c3, b3, a3, a4, c4, br f2, e1, e2, d1, d2, c1, c2, b1, b2, a2, b3, a3, b4, a4, a6, a7 f2, e1, e2, d1, d2, c1, c2, b1, b2, a2, b3, a3, b4, a4, a6, a7 f2, e1, e2, d1, d2, c1, c2, b1, b2, a2, b3, a3, b4, a4, a6, a7 tcrclk petpu2 ? ? 12 e3 f1 f1 f1 utpuodis petpu1 ? ? ? h10 j13 j13 j13 ltpuodis petpu0 ? ? ? g10 j14 j14 j14 fec emdio pfeci2c2 i2c_sda u2rxd i/o ? ? ?c7c7 emdc pfeci2c3 i2c_scl u2txd o ? ? ?d7d7 ecol ? ? ? i ? ? ?f3f3 table 2. mcf523x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5232 160 qfp mcf5232 196 mapbga mcf5233 256 mapbga mcf5234 256 mapbga mcf5235 256 mapbga
signal descriptions mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 7 ecrs ? ? ? i ? ? ?f4f4 erxclk ? ? ? i ? ? ?e3e3 erxdv ? ? ? i ? ? ?e4e4 erxd[3:0] ? ? ? i ? ? ?d3, d4, c3, c4 d3, d4, c3, c4 erxer ? ? ? i ? ? ?d5d5 etxclk ? ? ? i ? ? ?c5c5 etxen ? ? ? o ? ? ?d6d6 etxer ? ? ? o ? ? ?c6c6 etxd[3:0] ? ? ? o ? ? ? b6, b5, a5, b7 b6, b5, a5, b7 feature control etpu/ethenb ? ? ? i ????m4 i 2 c i2c_sda pfeci2c1 can0rx ? i/o ? j12 l15 l15 l15 i2c_scl pfeci2c0 can0tx ? i/o ? j11 l14 l14 l14 dma dack[2:0] and dreq [2:0] do not have a dedicated bond pads. please refer to the following pins for muxing: ts and dt2out for dack2, ts iz1and dt1out for dack1, tsiz0 and dt0out for dack0, irq2 and dt2in for dreq2 , tea and dt1in for dreq1 , and tip and dt0in for dreq0 . ? ? ? ? ? qspi qspi_cs1 pqspi4 sd_cke ? o 139 b7 b10 b10 b10 qspi_cs0 pqspi3 ? ? o 147 a6 d9 d9 d9 qspi_clk pqspi2 i2c_scl ? o 148 c5 b8 b8 b8 qspi_din pqspi1 i2c_sda ? i 149 b5 c8 c8 c8 qspi_dout pqspi0 ? ? o 150 a5 d8 d8 d8 uarts u2txd puarth1 can1tx ? o ?a8d11d11d11 u2rxd puarth0 can1rx ? i ?a7d10d10d10 u1cts puartl7 u2cts ? i ?b8c11c11c11 u1rts puartl6 u2rts ? o ?c8b11b11b11 u1txd puartl5 can0tx ? o 135 d9 a12 a12 a12 table 2. mcf523x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5232 160 qfp mcf5232 196 mapbga mcf5233 256 mapbga mcf5234 256 mapbga mcf5235 256 mapbga
mcf523x integrated microprocessor hardware specification, rev. 2 signal descriptions freescale semiconductor 8 u1rxd puartl4 can0rx ? i 136 d8 a11 a11 a11 u0cts puartl3 ? ? i ? f3 g1g1g1 u0rts puartl2 ? ? o ?g3h3h3h3 u0txd puartl1 ? ? o 14 f1 h2 h2 h2 u0rxd puartl0 ? ? i 13 f2 g2 g2 g2 dma timers dt3in ptimer7 u2cts qspi_cs2 i ? h14 j15 j15 j15 dt3out ptimer6 u2rts qspi_cs3 o ? g14 j16 j16 j16 dt2in ptimer5 dreq2 dt2out i ?m9p10p10p10 dt2out ptimer4 dack2 ? o ?l9r10r10r10 dt1in ptimer3 dreq1 dt1out i ?l6p7p7p7 dt1out ptimer2 dack1 ? o ?m6r7r7r7 dt0in ptimer1 dreq0 ? i ? e4 g4g4g4 dt0out ptimer0 dack0 ? o ? f4 g3g3g3 bdm/jtag 2 dsclk ? trst ? i 70 n9 n11 n11 n11 pstclk ? tclk ? o 68 p9 t10 t10 t10 bkpt ? tms ? i 71 p10 p11 p11 p11 dsi ? tdi ? i 73 m10 t11 t11 t11 dso ? tdo ? o 72 n10 r11 r11 r11 jtag_en ? ? ? i 78 k9 n13 n13 n13 ddata[3:0] ? ? ? o ?m12, n12, p12, l11 n14, p14, t13, r13 n14, p14, t13, r13 n14, p14, t13, r13 pst[3:0] ? ? ? o 77:74 m11, n11, p11, l10 t12, r12, p12, n12 t12, r12, p12, n12 t12, r12, p12, n12 table 2. mcf523x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5232 160 qfp mcf5232 196 mapbga mcf5233 256 mapbga mcf5234 256 mapbga mcf5235 256 mapbga
design recommendations mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 9 5 design recommendations 5.1 layout ? use a 4-layer printed circuit board with the v dd and gnd pins connected directly to the power and ground planes for the mcf523 x . ? see application note an1259, system design and layout techni ques for noise reduction in processor-based systems . ? match the pc layout trace width and routing to match trace length to operating frequency and board impedance. add termination (series or therein) to the traces to dampen reflections. increase the pcb impedance (if possible) keeping the trace lengt hs balanced and short. then do cross-talk analysis to separate traces with significant parall elism or are otherwise "noisy". use 6 mils trace and separation. clocks get extra sepa ration and more precise balancing. test test ? ? ? i 18 f5 j4 j4 j4 pll_test ? ? ? i ?r14r14r14 power supplies vddpll ? ? ? i 87 m13 p15 vsspll ? ? ? i 84 l14 r15 ovdd ? ? ? i 1, 9, 17, 32, 41, 55, 62, 69, 81, 90, 95, 105, 114, 128, 132, 138, 146 e5, e7, e10, f7, f9, g6, g8, h7, h8, h9, j6, j8, j10, k5, k6, k8 e6:11, f5, f7:10, f12, g5, g6, g11, g12, h5, h6, h11, h12, j5, j6, j11, j12, k5, k6, k11, k12, l5, l7:10, l12, m6:m11 vss ? ? ? i 8, 16, 25, 31, 40, 54, 61, 67, 80, 88, 94, 104, 113, 127, 131, 137, 145, 153, 160 a1, a14, e6, e9, f6, f8, f10, g7, g9, h6, j5, j7, j9, k7, p1, p14 a1, a16, e5, e12, f6, f11, f16, g7:10, h7: 10, j1, j7:10, k7:10, l6, l11, m5, m12, n16, t1, t6, t16 vdd ? ? ? i 15, 53, 103, 144 d6, f11, g4, l4 a8, g16, h1, t5 1 refers to pin?s primary function. all pins which are configurab le for gpio have a pullup enabled in gpio mode with the exceptio n of pbusctl[7], pbusctl[4: 0], paddr, pbs, psdram. 2 if jtag_en is asserted, these pins default to alternate 1 (jtag) functionality. the gpio module is not responsible for assignin g these pins. table 2. mcf523x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5232 160 qfp mcf5232 196 mapbga mcf5233 256 mapbga mcf5234 256 mapbga mcf5235 256 mapbga
mcf523x integrated microprocessor hardware specification, rev. 2 design recommendations freescale semiconductor 10 5.2 power supply ?33 f, 0.1 f, and 0.01 f across each power supply 5.2.1 supply voltage sequencing and separation cautions figure 1 shows situations in sequencing the i/o v dd (ov dd ), pll v dd (pllv dd ), and core v dd (v dd ). ov dd is specified relative to v dd . figure 1. supply voltage sequencing and separation cautions 5.2.1.1 power up sequence if ov dd are powered up with v dd at 0 v, then the sense circuits in th e i/o pads will ca use all pad output drivers connected to the ov dd to be in a high impedance state. there is no limit on how long after ov dd powers up before v dd must powered up. v dd should not lead the ov dd or pllv dd by more than 0.4 v during power ramp-up, or there will be high current in the internal es d protection diodes. the rise times on the power supplies should be slower than 1 s to avoid turning on the in ternal esd protection clamp diodes. the recommended power up sequence is as follows: 1. use 1 s or slower rise time for all supplies. 2. v dd /pllv dd and ov dd should track up to 0.9 v, then separate for the completion of ramps with ov dd going to the higher external voltages. one way to accomplish this is to use a low drop-out voltage regulator. supplies stable 2 1 3.3v 2.5v 1.5v 0 time notes: vdd should not exceed ovdd or pllvdd by more than 0.4 v at any time, including power-up. recommended that vdd/pllvdd should track ovdd up to 0.9 v, then separate for completion of ramps. input voltage must not be greater than the supply voltage (ovdd, vdd, or pllvdd) by more than 0.5 v at any time, including during power-up. use 1 ms or slower rise time for all supplies. 1. 2. 3. 4. dc power supply voltage v dd , pllv dd ov dd
design recommendations mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 11 5.2.1.2 power down sequence if v dd /pllv dd are powered down first, then se nse circuits in the i/o pads wi ll cause all output drivers to be in a high impedance state. th ere is no limit on how long after v dd and pllv dd power down before ov dd must power down. v dd should not lag ov dd or pllv dd going low by more than 0.4 v during power down or there will be unde sired high current in the esd protection diodes. there are no requirements for the fall ti mes of the power supplies. the recommended power down sequence is as follows: 1. drop v dd /pllv dd to 0 v. 2. drop ov dd supplies. 5.3 decoupling ? place the decoupling caps as close to the pins as possible, but they can be outside the footprint of the package. ? 0.1 f and 0.01 f at each supply input 5.4 buffering ? use bus buffers on all data/address lines for al l off-board accesses and for all on-board accesses when excessive loading is expected. see section 7, ?preliminary electrical characteristics .? 5.5 pull-up recommendations ? use external pull-up resistors on unused inputs. see pin table. 5.6 clocking recommendations ? use a multi-layer board wi th a separate ground plane. ? place the crystal and all other as sociated components as close to the extal and xtal (oscillator pins) as possible. ? do not run a high frequency trace around crystal circuit. ? ensure that the ground for the bypass capaci tors is connected to a solid ground trace. ? tie the ground trace to the ground pi n nearest extal and xtal. this prevents large loop currents in the vicinity of the crystal. ? tie the ground pin to the most solid ground in the system. ? do not connect the trace that connects the oscill ator and the ground plane to any other circuit element. this tends to ma ke the oscillator unstable. ? tie xtal to ground when an external oscillator is clocking the device.
mcf523x integrated microprocessor hardware specification, rev. 2 design recommendations freescale semiconductor 12 5.7 interface recommendations 5.7.1 sdram controller 5.7.1.1 sdram controller si gnals in synchronous mode table 3 shows the behavior of sdram signals in synchronous mode. 5.7.1.2 address multiplexing see the sdram controller module chapter in the mcf5235 reference manual for details on address multiplexing. 5.7.2 ethernet phy transceiver connection the fec supports both an mii interfac e for 10/100 mbps ethernet and a se ven-wire serial interface for 10 mbps ethernet. the interface mode is select ed by r_cntrl[mii_mode]. in mii mode, the 802.3 standard defines and the fec module s upports 18 signals. these are shown in table 4 . table 3. synchronous dram signal connections signal description sd_sras synchronous row address strobe. indicates a va lid sdram row address is present and can be latched by the sdram. sd_sras should be connected to the corresponding sdram sd_sras . do not confuse sd_sras with the dram controller?s sd_cs [1:0], which should not be interfaced to the sdram sd_sras signals. sd_scas synchronous column address strobe. indicates a valid column address is present and can be latched by the sdram. sd_scas should be connected to the corresponding signal labeled sd_scas on the sdram. dramw dram read/write. asserted for write operations and negated for read operations. sd_cs [1:0] row address strobe. select each memory block of sdrams connected to the mcf523 x . one sd_cs signal selects one sdram block and connects to the corresponding cs signals. sd_cke synchronous dram clock enable. connected directly to the cke (clock enable) signal of sdrams. enables and disables the clock internal to sdram. when cke is low, memory can enter a power-down mode where operations are su spended or they can enter self-refresh mode. sd_cke functionality is controlled by dcr[coc]. for designs using external multiplexing, setting coc allows sd_cke to prov ide command-bit functionality. bs [3:0] column address strobe. for synchronous operation, bs [3:0] function as byte enables to the sdrams. they connect to the dqm signals (or mask qualifiers) of the sdrams. clkout bus clock output. connects to the clk input of sdrams. table 4. mii mode signal description mcf523 x pin transmit clock etxclk transmit enable etxen transmit data etxd[3:0]
design recommendations mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 13 the serial mode interface operates in what is generally referred to as amd mode. the mcf523 x configuration for seven-wire seri al mode connections to the exte rnal transceiver are shown in table 5 . refer to the m523 x evb evaluation board user?s manual for an example of how to connect an external phy. schematics for this board are accessible at the mcf523 5 site by navigating to: http://www.freesca le.com/coldfire . transmit error etxer collision ecol carrier sense ecrs receive clock erxclk receive enable erxdv receive data erxd[3:0] receive error erxer management channel clock emdc management channel serial data emdio table 5. seven-wire mode configuration signal description mcf523 x pin transmit clock etxclk transmit enable etxen transmit data etxd[0] collision ecol receive clock erxclk receive enable erxdv receive data erxd[0] unused, configure as pb14 erxer unused input, tie to ground ecrs unused, configure as pb[13:11] erxd[3:1] unused output, ignore etxer unused, configure as pb[10:8] etxd[3:1] unused, configure as pb15 emdc input after reset, connect to ground emdio table 4. mii mode (continued) signal description mcf523 x pin
mcf523x integrated microprocessor hardware specification, rev. 2 mechanicals/pinouts and part numbers freescale semiconductor 14 5.7.3 flexcan the flexcan module interface to the can bus is co mposed of 2 pins: cantx and canrx, which are the serial transmitted data and the serial received data. the use of an external can transceiver to interface to the can bus is generally required. the transceiver is capable of driv ing the large current needed for the can bus and has current protection, against a defective can bus or defective stations. 5.7.4 bdm use the bdm interface as shown in the m523 x evb evaluation board user?s manual. the schematics for this board are accessible at the freescale website at: http://www.freescale.com/coldfire . 6 mechanicals/pinouts and part numbers this section contains drawings s howing the pinout and the packaging a nd mechanical char acteristics of the mcf523 x devices. see table 2 for a list the signal names and pin locations for each device. 6.1 pinout?196 mapbga the following figure shows a pinout of the mcf5232cvmxxx package.
mechanicals/pi nouts and part numbers mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 15 figure 2. mcf5232cvmxxx pinout (196 mapbga) 6.2 package dimensions?196 mapbga figure 3 shows mcf5232cvmxxx package dimensions. 1234567891011121314 a vss tpuch6 tpuch3 tpuch2 qspi_ dout qspi_cs0 u2rxd u2txd cs3 cs6 cs4 a20 a17 vss a b tpuch8 tpuch7 tpuch4 tpuch0 qspi_ din bs3 qspi_cs1 u1cts cs7 cs1 a23 a19 a16 a15 b c tpuch10 tpuch9 tpuch5 tpuch1 qspi_clk bs2 bs0 u1rts cs2 cs5 a22 a18 a14 a13 c d tpuch13 tpuch12 tpuch11 nc nc vdd bs1 u1rxd/ can0rx u1txd/ can0tx cs0 a21 a12 a11 a10 d e tpuch14 tpuch15 tcrclk dt0in ovdd vss ovdd sd_cke vss ovdd a9 a8 a7 a6 e f u0txd u0rxd u0cts dt0out test vss ovdd vss ovdd vss vdd a5 a4 a3 f g d31 d30 u0rts vdd clkmod1 ovdd vss ovdd vss ltpu odis a2 a1 a0 dt3out g h d29 d28 d27 d26 clkmod0 vss ovdd ovdd ovdd utpu odis ta tip ts dt3in h j d25 d24 d23 d22 vss ovdd vss ovdd vss ovdd i2c_scl i2c_sda r/w tea j k d21 d20 d19 d18 ovdd ovdd vss ovdd jtag_en rcon sd_sras sd_scas sd_we clkout k l d17 d16 d10 vdd d3 dt1in irq5 irq1 dt2out pst0 ddata0 sd_cs1 sd_cs0 vsspll l m d15 d13 d9 d6 d2 dt1out irq6 irq2 dt2in tdi/dsi pst3 ddata3 vddpll extal m n d14 d12 d8 d5 d1 oe irq7 irq3 trst / dsclk tdo/dso pst2 ddata2 reset xtal n p vss d11 d7 d4 d0 tsiz1 tsiz0 irq4 tclk/ pstclk tms/ bkpt pst1 ddata1 rstout vss p 1234567891011121314
mcf523x integrated microprocessor hardware specification, rev. 2 mechanicals/pinouts and part numbers freescale semiconductor 16 figure 3. 196 mapbga package dimensions (case no. 1128a-01) 6.2.1 pinout?256 mapbga figure 4 through figure 6 show pinouts of the mcf5233cvmxxx, mcf5234cvmxxx, and mcf5235cvmxxx packages. x tol laser mark for pin 1 identification in this area e 13x d e m s a1 a2 a 0.10 z 0.20 z z rotated 90 clockwise detail k 5 view m-m e 13x s m x 0.15 y z 0.08 z 3 b 196x metalized mark for pin 1 identification in this area 14 13 12 11 5 4 3 2 b c d e f g h j k l 4 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. y k m n p a 1 6 10 9 dim millimeters min max a 1.25 1.60 a1 0.27 0.47 a2 1.16 ref b 0.45 0.55 d 15.00 bsc e 15.00 bsc e 1.00 bsc s 0.50 bsc 196x
mechanicals/pi nouts and part numbers mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 17 figure 4. mcf5233cvmxxx pinout (256 mapbga) 1 2 3 4 5 6 7 8 9 10111213 14 15 16 a vss tpuch6 tpuch4 tpuch2 tpuch17 tpuch1 tpuch0 vdd bs1 bs0 u1rxd/ can0rx u1txd/ can0tx cs6 cs4 a21 vss a b tpuch8 tpuch7 tpuch5 tpuch3 tpuch18 tpuch19 tpuch16 qspi_ clk bs2 qspi_ cs1 u1rts cs3 cs1 a23 a20 a19 b c tpuch10 tpuch9 tpuch25 tpuch24 tpuch22 tpuch20 i2c_sda/ u2rxd qspi_ din bs3 sd_cke u1cts cs7 cs5 a22 a18 a17 c d tpuch12 tpuch11 tpuch27 tpuch26 tpuch23 tpuch21 i2c_scl/ u2txd qspi_ dout qspi_ cs0 u2rxd/ can1rx u2txd/ can1tx cs2 cs0 a14 a15 a16 d e tpuch14 tpuch13 tpuch29 tpuch28 vss ovdd ovdd ovdd ovdd ovdd ovdd vss a10 a11 a12 a13 e f tcrclk tpuch15 tpuch31 tpuch30 ovdd vss ovdd ovdd ovdd ovdd vss ovdd a7 a8 a9 vss f g u0cts u0rxd dt0out dt0in ovdd ovdd vss vss vss vss ovdd ovdd a4 a5 a6 vdd g h vdd u0txd u0rts nc ovdd ovdd vss vss vss vss ovdd ovdd a0 a1 a2 a3 h j vss clk mod0 clk mod1 test ovdd ovdd vss vss vss vss ovdd ovdd utpu odis ltpu odis dt3in dt3out j k d28 d29 d30 d31 ovdd ovdd vss vss vss vss ovdd ovdd tea ta tip ts k l d24 d25 d26 d27 ovdd vss ovdd ovdd ovdd ovdd vss ovdd sd_we i2c_scl/ can0tx i2c_sda/ can0rx r/w l m d21 d22 d23 nc vss ovdd ovdd ovdd ovdd ovdd ovdd vss sd_ cs0 sd_ sras sd_ scas clkout m n d19 d20 d13 d9 nc d3 d0 tsiz1 irq5 irq1 trst / dsclk pst0 jtag_ en ddata3 sd_cs1 vss n p d17 d18 d12 d8 d5 d2 dt1in tsiz0 irq4 dt2in tms/ bkpt pst1 rcon ddata2 vddpll extal p r d16 d15 d11 d7 d4 d1 dt1out irq7 irq3 dt2out tdo/ dso pst2 ddata0 pll_ test vsspll xtal r t vss d14 d10 d6 vdd vss oe irq6 irq2 tclk/ pstclk tdi/dsi pst3 ddata1 rstout reset vss t 1 2 3 4 5 6 7 8 9 10111213 14 15 16
mcf523x integrated microprocessor hardware specification, rev. 2 mechanicals/pinouts and part numbers freescale semiconductor 18 figure 5. mcf5234cvmxxx pinout (256 mapbga) 1 2 3 4 5 6 7 8 9 10111213 14 15 16 a vss tpuch6 tpuch4 tpuch2 etxd1 tpuch1 tpuch0 vdd bs1 bs0 u1rxd/ can0rx u1txd/ can0tx cs6 cs4 a21 vss a b tpuch8 tpuch7 tpuch5 tpuch3 etxd2 etxd3 etxd0 qspi_ clk bs2 qspi_ cs1 u1rts cs3 cs1 a23 a20 a19 b c tpuch10 tpuch9 erxd1 erxd0 etxclk etxer emdio qspi_ din bs3 sd_cke u1cts cs7 cs5 a22 a18 a17 c d tpuch12 tpuch11 erxd3 erxd2 erxer etxen emdc qspi_ dout qspi_ cs0 u2rxd u2txd cs2 cs0 a14 a15 a16 d e tpuch14 tpuch13 erxclk erxdv vss ovdd ovdd ovdd ovdd ovdd ovdd vss a10 a11 a12 a13 e f tcrclk tpuch15 ecol ecrs ovdd vss ovdd ovdd ovdd ovdd vss ovdd a7 a8 a9 vss f g u0cts u0rxd dt0out dt0in ovdd ovdd vss vss vss vss ovdd ovdd a4 a5 a6 vdd g h vdd u0txd u0rts nc ovdd ovdd vss vss vss vss ovdd ovdd a0 a1 a2 a3 h j vss clk mod0 clk mod1 test ovdd ovdd vss vss vss vss ovdd ovdd utpu odis ltpu odis dt3in dt3out j k d28 d29 d30 d31 ovdd ovdd vss vss vss vss ovdd ovdd tea ta tip ts k l d24 d25 d26 d27 ovdd vss ovdd ovdd ovdd ovdd vss ovdd sd_we i2c_scl/ can0tx i2c_sda/ can0rx r/w l m d21 d22 d23 nc vss ovdd ovdd ovdd ovdd ovdd ovdd vss sd_cs0 sd_ sras sd_ scas clkout m n d19 d20 d13 d9 nc d3 d0 tsiz1 irq5 irq1 trst / dsclk pst0 jtag_ en ddata3 sd_cs1 vss n p d17 d18 d12 d8 d5 d2 dt1in tsiz0 irq4 dt2in tms/ bkpt pst1 rcon ddata2 vddpll extal p r d16 d15 d11 d7 d4 d1 dt1out irq7 irq3 dt2out tdo/ dso pst2 ddata0 pll_ test vsspll xtal r t vss d14 d10 d6 vdd vss oe irq6 irq2 tclk/ pstclk tdi/dsi pst3 ddata1 rst out reset vss t 1 2 3 4 5 6 7 8 9 10111213 14 15 16
mechanicals/pi nouts and part numbers mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 19 figure 6. mcf5235cvmxxx pinout (256 mapbga) 12345678910111213141516 a vss tpuch6 tpuch4 tpuch2 tpuch17/ etxd1 tpuch1 tpuch0 vdd bs1 bs0 u1rxd/ can0rx u1txd/ can0tx cs6 cs4 a21 vss a b tpuch8 tpuch7 tpuch5 tpuch3 tpuch18/ etxd2 tpuch19/ etxd3 tpuch16/ etxd0 qspi_ clk bs2 qspi_ cs1 u1rts cs3 cs1 a23 a20 a19 b c tpuch10 tpuch9 tpuch25/ erxd1 tpuch24/ erxd0 tpuch22/ etxclk tpuch20/ etxer i2c_sda/ u2rxd/ emdio qspi_ din bs3 sd_cke u1cts cs7 cs5 a22 a18 a17 c d tpuch12 tpuch11 tpuch27/ erxd3 tpuch26/ erxd2 tpuch23/ erxer tpuch21/ etxen i2c_scl/ u2txd/ emdc qspi_ dout qspi_ cs0 u2rxd/ can1rx u2txd/ can1tx cs2 cs0 a14 a15 a16 d e tpuch14 tpuch13 tpuch29/ erxclk tpuch2/ erxdv vss ovdd ovdd ovdd ovdd ovdd ovdd vss a10 a11 a12 a13 e f tcrclk tpuch15 tpuch31/ ecol tpuch30/ ecrs ovdd vss ovdd ovdd ovdd ovdd vss ovdd a7 a8 a9 vss f g u0cts u0rxd dt0out dt0in ovdd ovdd vss vss vss vss ovdd ovdd a4 a5 a6 vdd g h vdd u0txd u0rts nc ovdd ovdd vss vss vss vss ovdd ovdd a0 a1 a2 a3 h j vss clk mod0 clk mod1 test ovdd ovdd vss vss vss vss ovdd ovdd utpu odis ltpu odis dt3in dt3out j k d28 d29 d30 d31 ovdd ovdd vss vss vss vss ovdd ovdd tea ta tip ts k l d24 d25 d26 d27 ovdd vss ovdd ovdd ovdd ovdd vss ovdd sd_we i2c_scl/ can0tx i2c_sda/ can0rx r/w l m d21 d22 d23 etpu/ ethenb vss ovdd ovdd ovdd ovdd ovdd ovdd vss sd_cs0 sd_ sras sd_ scas clkout m n d19 d20 d13 d9 nc d3 d0 tsiz1 irq5 irq1 trst / dsclk pst0 jtag_ en ddata3 sd_cs1 vss n p d17 d18 d12 d8 d5 d2 dt1in tsiz0 irq4 dt2in tms/ bkpt pst1 rcon ddata2 vddpll extal p r d16 d15 d11 d7 d4 d1 dt1out irq7 irq3 dt2out tdo/ dso pst2 ddata0 pll_ test vsspll xtal r t vss d14 d10 d6 vdd vss oe irq6 irq2 tclk/ pstclk tdi/dsi pst3 ddata1 rstout reset vss t 12345678910111213141516
mcf523x integrated microprocessor hardware specification, rev. 2 mechanicals/pinouts and part numbers freescale semiconductor 20 6.2.2 package dimensions?256 mapbga figure 7 shows mcf5235cvmxxx, mcf 5234cvmxxx, and mcf5233cvmxx package dimensions. figure 7. 256 mapbga package outline 6.3 pinout?160 qfp figure 8 shows a pinout of the mcf5232cabxxx package. x y d e laser mark for pin a1 identification in this area 0.20 metalized mark for pin a1 identification in this area m m 3 a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 10 11 12 13 14 15 16 e 15x e 15x b 256x m 0.25 y z m 0.10 x z s detail k view m-m rotated 90 clockwise s a z z a2 a1 4 0.15 z 0.30 256x 5 k notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.25 1.60 a1 0.27 0.47 a2 1.16 ref b 0.40 0.60 d 17.00 bsc e 17.00 bsc e 1.00 bsc s 0.50 bsc
mechanicals/pi nouts and part numbers mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 21 figure 8. mcf5232cabxxx pinout (160 qfp) 6.4 package dimensions?160 qfp figure 9 shows mcf5232cab80 package dimensions. 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vss tpuch7 tpuch6 tpuch5 tpuch4 tpuch3 tpuch2 vss tpuch1 tpuch0 qspi_dout qspi_din qspi_clk qspi_cs0 ovdd vss\ovss vdd bs3 bs2 bs1 bs0 sd_cke\qspi_cs1 ovdd vss u1rxd\can0rx u1txd\can0tx cs3 cs2 ovdd vss cs1 cs0 ovdd vss a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 ovdd vss a11 a10 a9 a8 a7 a6 a5 ovdd vss/ovss vdd a4 a3 a2 a1 a0 ta r/w ovdd vss sd_we sd_scas sd_sras ovdd clkout vss vddpll extal xtal vsspll reset rstout /pll_test ovdd a23 ovdd tpuch8 tpuch9 tpuch10 tpuch11 tpuch12 tpuch13 vss ovdd tpuch14 tpuch15 tcrclk u0rxd u0txd vdd vss ovdd test clkmod1 clkmod0 d31 d30 d29 d28 vss d27 d26 d25 d24 d23 vss ovdd d22 d21 d20 d19 d18 d17 d16 vss ovdd d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 vdd vss\ovss ovdd d4 d3 d2 d1 d0 vss ovdd oe irq7 irq4 irq1 vss tclk\pstclk ovdd trst \dsclk tms\bkpt tdo/dso tdi/dsi pst0 pst1 pst2 pst3 jtag_en rcon vss mcf5232
mcf523x integrated microprocessor hardware specification, rev. 2 mechanicals/pinouts and part numbers freescale semiconductor 22 figure 9. 160 qfp package dimensions top & bottom case 864a-03 d n f j base metal section b?b detail c s s ?c? e c m u w k x q r t h ?h? b ?a?, ?b?, ?d? b detail a g p s s s s s s a s l z l y detail a b v ?a? ?b? ?h? detail c millimeters inches dim min max min max a b c d e f g h j k l m n p q r t u v w x y z 27.90 28.10 1.098 1.106 27.90 28.10 1.098 1.106 3.35 3.85 0.132 1.106 3.35 3.85 0.009 0.015 0.22 0.38 0.009 0.013 0.22 0.33 0.126 0.138 3.20 3.50 0.65 bsc 0.026 ref 0.010 0.014 0.25 0.35 0.004 0.009 0.11 0.23 0.028 0.035 0.70 0.90 25.35 bsc 0.998 ref 5 16 5 16 0.004 0.007 0.11 0.19 0.325 bsc 0.013 ref 0 7 0 7 0.005 0.012 0.13 0.30 0.005 ? 0.13 ? 0 ?0 ? 31.00 31.40 1.220 1.236 s 31.00 31.40 1.220 1.236 0.016 ? 0.4 ? 1.60 ref 0.063 ref 1.33 ref 0.052 ref 1.33 ref 0.052 ref notes 1. dimensioning and tolerincing per ansi y14.5m, 1982. 2. controlling dimension: millimeter 3. datum plan -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b-, and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. 0.110 (0.004) a-b d c 0.13 (0.005) m 0.20 (0.008) a-b d c m m 0.20 (0.008) a-b 0.20 (0.008) a-b d c s s m m h a-b d h a-b d 0.20 (0.008) 0.20 (0.008) 0.20 (0.008) a-b
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 23 6.5 ordering information 7 preliminary electrical characteristics this chapter contains electrical specification tabl es and reference timing diagrams for the mcf5235 microcontroller unit. this section contains deta iled information on power considerations, dc/ac electrical characteristi cs, and ac timing spec ifications of mcf5235. the electrical specifications are preliminary and are from previous designs or design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specificat ions will be met. finalized speci fications will be published after complete characterization and device qualifications have been completed. note the parameters specified in this pr ocessor document supe rsede any values found in the module specifications. 7.1 maximum ratings table 6. orderable part numbers freescale part number description speed temperature mcf5232cab80 mcf5232 risc microprocessor, 160 qfp 80mhz ?40 to +85 c mcf5232cvm100 mcf5232 risc microprocessor, 196 mapbga 100mhz ?40 to +85 c mcf5232cvm150 mcf5232 risc microprocessor, 196 mapbga 150mhz ?40 to +85 c mcf5233cvm100 mcf5233 risc microprocessor, 256 mapbga 100mhz ?40 to +85 c mcf5233cvm150 mcf5233 risc microprocessor, 256 mapbga 150mhz ?40 to +85 c MCF5234CVM100 mcf5234 risc microprocessor, 256 mapbga 100mhz ?40 to +85 c mcf5234cvm150 mcf5234 risc microprocessor, 256 mapbga 150mhz ?40 to +85 c mcf5235cvm100 mcf5235 risc microprocessor, 256 mapbga 100mhz ?40 to +85 c mcf5235cvm150 mcf5235 risc microprocessor, 256 mapbga 150mhz ?40 to +85 c table 7. absolute maximum ratings 1, 2 rating symbol value unit core supply voltage v dd ? 0.5 to +2.0 v pad supply voltage ov dd ? 0.3 to +4.0 v clock synthesizer supply voltage v ddpll ? 0.3 to +4.0 v digital input voltage 3 v in ? 0.3 to + 4.0 v
mcf523x integrated microprocessor hardware specification, rev. 2 preliminary electrical characteristics freescale semiconductor 24 7.2 thermal characteristics the below table lists thermal resistance values. instantaneous maximum current single pin limit (applies to all pins) 3,4,5 i d 25 ma operating temperatur e range (packaged) t a (t l - t h ) ? 40 to 85 c storage temperature range t stg ? 65 to 150 c 1 functional operating conditions are given in dc electrical specifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. continued operation at these levels may affect device reliability or cause permanent damage to the device. 2 this device contains circuitry protecting a gainst damage due to high static voltage or electrical fields; however, it is advised that no rmal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or ov dd ). 3 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 all functional non-supply pins are internally clamped to v ss and ov dd . 5 power supply must maintain regulation within operating ov dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > ov dd ) is greater than i dd , the injection current may flow out of ov dd and could result in external power supply going out of regulation . insure external ov dd load will shunt current greater than maximum injection current. this will be the greatest risk when the processor is not consuming power (ex; no clock).power supply must maintain regulation within operating ov dd range during instantaneous and operating maximum current conditions. table 8. thermal characteristics characteristic symbol 256 mapbga 196 mapbga 160 qfp unit junction to ambient, natural convection four layer board (2s2p) jma 26 1,2 1 jma and jt parameters are simulated in conformance with eia/j esd standard 51-2 for natural convection. freescale recommends the use of jma and power dissipation specif ications in the system design to prevent device junction temperatures from exceeding the rate d specification. system designers sh ould be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. conformance to the device junction temperature specification c an be verified by physical measurement in the customer?s system using the jt parameter, the device power dissipation, and th e method described in eia/jesd standard 51-2. 2 per jedec jesd51-6 with the board horizontal. 32 1,2 40 1,2 c / w junction to ambient (@200 ft/min) four layer board (2s2p) jma 23 1,2 29 1,2 36 1,2 c / w junction to board jb 15 3 20 3 25 3 c / w junction to case jc 10 4 10 4 10 4 c / w junction to top of package jt 2 1,5 2 1,5 2 1,5 c / w maximum operating junction temperature t j 102 104 105 6o c table 7. absolute maximum ratings 1, 2 (continued) rating symbol value unit
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 25 7.3 dc electrical specifications 3 thermal resistance between the die and the printed ci rcuit board in conformance with jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 4 thermal resistance between the die and the case top surfac e as measured by the cold plate method (mil spec-883 method 1012.1). 5 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written in conformance with psi-jt. 6 at 100mhz. the average chip-junction temperature (t j ) in c can be obtained from: (1) where: t a = ambient temperature, c jma = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts - chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o < p int and can be ignored. an appr oximate relations hip between p d and t j (if p i/o is neglected) is: (2) solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + jma p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . table 9. dc electrical specifications 1 characteristic symbol min typical max unit core supply voltage v dd 1.4 ? 1.6 v pad supply voltage ov dd 3?3.6v input high voltage v ih 0.7 ov dd ?3.65v input low voltage v il v ss ? 0.3 ? 0.35 ov dd v input hysteresis v hys 0.06 ov dd ??mv input leakage current v in = v dd or v ss , input-only pins i in ?1.0 ? 1.0 a high impedance (off-state) leakage current v in = v dd or v ss , all input/output and output pins i oz ?1.0 ? 1.0 a t j t a p d jma () + = p d kt j 273 c + () =
mcf523x integrated microprocessor hardware specification, rev. 2 preliminary electrical characteristics freescale semiconductor 26 output high voltage (all input/ output and all output pins) i oh = ?5.0 ma v oh ov dd - 0.5 ? ? v output low voltage (all inpu t/output and all output pins) i ol = 5.0ma v ol ??0.5v weak internal pull up device current, tested at v il max. 2 i apu ?10 ? ? 130 a input capacitance 3 all input-only pins all input/output (three-state) pins c in ? ? ? 7 7 pf load capacitance 4 low drive strength high drive strength c l ? ? 25 50 pf pf core operating supply current 5 master mode i dd ? 135 150 ma pad operating supply current master mode low power modes oi dd ? ? 100 tbd ? ? ma a dc injection current 3, 6, 7, 8 v negclamp =v ss ? 0.3 v, v posclamp = v dd + 0.3 single pin limit total processor limit, include s sum of all stressed pins i ic ?1.0 ?10 1.0 10 ma ma 1 refer to table 10 for additional pll specifications. 2 refer to the mcf5235 signals section for pins having weak internal pull-up devices. 3 this parameter is characterized before qualification rather than 100% tested. 4 pf load ratings are based on dc loading and are provided as an indication of driver strength. high speed interfaces require transmission line analysis to determine proper drive strength and termination. see high speed signal propagation: advanced black magic by howard w. johnson for design guidelines. 5 current measured at maximum system clock frequency, all modu les active, and default drive strength with matching load. 6 all functional non-supply pins are internally clamped to v ss and their respective v dd . 7 input must be current limited to the value specified. to dete rmine the value of the required current-limiting resistor, calcula te resistance values for positive and negative clamp voltages, then use the larger of the two values. 8 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. insure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the pr ocessor is not consuming power. examples are: if no system clock is present, or if clock rate is very low which would r educe overall power consumption. also, at power-up, system clock is not present during the power-up sequence until the pll has attained lock. table 9. dc electrical specifications 1 (continued) characteristic symbol min typical max unit
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 27 7.4 oscillator and pllmrfm electrical characteristics table 10. hip7 pllmrfm electrical specifications 1 1 all values given are initial design targets and subject to change. num characteristic symbol min. value max. value unit 1 pll reference frequency range crystal reference external reference 1:1 mode (note: f sys/2 = 2 f ref_1:1 ) f ref_crystal f ref_ext f ref_1:1 8 8 24 25 25 75 mhz 2 core frequency clkout frequency 2 external reference on-chip pll frequency 2 all internal registers retain data at 0 hz. f sys f sys/2 0 f ref 32 150 75 75 mhz mhz mhz 3 loss of reference frequency 3, 5 3 ?loss of reference frequency? is the reference fre quency detected internally, which transitions the pll into self clocked mode. f lor 100 1000 khz 4 self clocked mode frequency 4, 5 4 self clocked mode frequency is the frequency that th e pll operates at when the reference frequency falls below f lor with default mfd/rfd settings. f scm 10.25 15.25 mhz 5 crystal start-up time 5, 6 5 this parameter is guaranteed by characteriza tion before qualification rather than 100% tested. 6 proper pc board layout procedures must be followed to achieve specifications. t cst ?10ms 6 xtal load capacitance 5 530pf 7 pll lock time 5, 7,13 t lpll ?750 s 8 power-up to lock time 5, 6,8 with crystal reference (includes 5 time) without crystal reference 9 t lplk ? ? 11 750 ms s 9 1:1 mode clock skew (between clkout and extal) 10 t skew ?1 1 ns 10 duty cycle of reference 5 t dc 40 60 % 11 frequency un-lock range f ul ?3.8 4.1 % f sys/2 12 frequency lock range f lck ?1.7 2.0 % f sys/2 13 clkout period jitter, 5, 6, 8,11, 12 measured at f sys/2 max peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over 2 ms interval) c jitter ? ? 5.0 .01 % f sys/2 14 frequency modulation range limit 13,14 (f sys/2 max must not be exceeded) c mod 0.8 2.2 %f sys/2 15 ico frequency. f ico = f ref 2 (mfd+2) 15 f ico 48 150 mhz
mcf523x integrated microprocessor hardware specification, rev. 2 preliminary electrical characteristics freescale semiconductor 28 7.5 external interface timing characteristics table 11 lists processor bus input timings. note all processor bus timings are synchr onous; that is, input setup/hold and output delay with respect to the ri sing edge of a reference clock. the reference clock is the clkout output. all other timing relationships ca n be derived fro m these values. timings listed in table 11 are shown in figure 10 & figure a-3. 7 this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesiz er control register (syncr). 8 assuming a reference is available at power up , lock time is measured from the time v dd and v ddsyn are valid to rstout negating. if the crystal oscillator is being us ed as the reference for the pll, then the crystal start up time must be added to the pll lock time to determine the total start-up time. 9 t lpll = (64 * 4 * 5 + 5 ) t ref , where t ref = 1/f ref_crystal = 1/f ref_ext = 1/f ref_1:1 , and = 1.57x10 -6 2(mfd + 2). 10 pll is operating in 1:1 pll mode. 11 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys/2 . measurements are made with the device po wered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v sssyn and variation in crystal oscillator frequency increase the cjitter percentage for a given interval. 12 values are with frequency modulation disabled. if frequency modulation is enabled, jitter is the sum of cjitter+cmod. 13 modulation percentage applies over an interval of 10 s, or equivalently the modulation rate is 100khz. 14 modulation rate selected must not result in f sys/2 value greater than the f sys/2 maximum specified value. modulation range determined by hardware design. 15 f sys/2 = f ico / (2 * 2 rfd ) table 11. processor bus input timing specifications name characteristic 1 1 timing specifications are tested using full drive st rength pad configurations in a 50ohm transmission line environment.. symbol min max unit freq system bus frequency f sys/2 50 75 mhz b0 clkout period t cyc ?1/75ns control inputs b1a control input valid to clkout high 2 2 tea and ta pins are being referred to as control inputs. t cvch 9?ns b1b bkpt valid to clkout high 3 3 refer to figure a-19. t bkvch 9?ns b2a clkout high to control inputs invalid 2 t chcii 0?ns b2b clkout high to asynch ronous cont rol input bkpt invalid 3 t bknch 0?ns data inputs b4 data input (d[31:0]) valid to clkout high t divch 4?ns b5 clkout high to data input (d[31:0]) invalid t chdii 0?ns
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 29 figure 10. general input timing requirements 7.6 processor bus output timing specifications table 12 lists processor bus output timings. table 12. external bus output timing specifications name characteristic symbol min max unit control outputs b6a clkout high to chip selects valid 1 t chcv ?0.5t cyc +5 ns b6b clkout high to byte enables (bs [3:0]) valid 2 t chbv ?0.5t cyc +5 ns b6c clkout high to output enable (oe ) valid 3 t chov ?0.5t cyc +5 ns b7 clkout high to control output (bs [3:0], oe ) invalid t chcoi 0.5t cyc +1.5 ? ns b7a clkout high to chip selects invalid t chci 0.5t cyc +1.5 ? ns address and attribute outputs b8 clkout high to address (a[23:0]) and control (ts , tsiz [1:0], tip , r/w) valid t chav ?9ns invalid invalid clkout(75mhz) t setup t hold input setup and hold 1.5v trise v h = v ih v l = v il 1.5v 1.5v valid tfall v h = v ih v l = v il input rise time input fall time * the timings are also valid for inputs sampled on the negative clock edge. inputs clkout b4 b5
mcf523x integrated microprocessor hardware specification, rev. 2 preliminary electrical characteristics freescale semiconductor 30 read/write bus timings listed in table 12 are shown in figure 11 , figure 12 , and figure 13 . figure 11. read/write (internally terminated) sram bus timing b9 clkout high to address (a[23:0]) and control (ts , tsiz [1:0], tip , r/w) invalid t chai 1.5 ? ns data outputs b11 clkout high to data output (d[31:0]) valid t chdov ?9ns b12 clkout high to data output (d[31:0]) invalid t chdoi 1.5 ? ns b13 clkout high to data output (d[31:0]) high impedance t chdoz ?9ns 1 cs transitions after the falling edge of clkout. 2 bs transitions after the falling edge of clkout. 3 oe transitions after the falling edge of clkout. table 12. external bus output timing specifications (continued) name characteristic symbol min max unit b12 b13 b8 clkout csn a[23:0] r/w bs [3:0] d[31:0] ta (h) (h) s0 s2 s3 s1 s4 s5 s0 s1 s2 s3 s4 s5 tea (h) b6a b8 b7a b6c b7 b6b b7 b4 b5 b11 b9 b9 b6b oe b0 b7 b9 ts tip b8 b8 b9 b8 b9 tsiz [1:0] b7a b6a b8
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 31 figure 12 shows a bus cycle terminated by ta showing timings listed in table 12 . figure 12. sram read bus cycle terminated by ta figure 13 shows an sram bus cycle terminated by tea showing timings listed in table 12 . b8 b9 b6a clkout cs n a[23:0] oe r/w bs [3:0] ta (h) s0 s2 s3 s1 s4 s5 s0 s1 tea (h) b8 b7a b9 b6c b7 b6b b7 b2a b1a d[31:0] b4 b5 b8 ts b9 tip tsiz[ 1:0]
mcf523x integrated microprocessor hardware specification, rev. 2 preliminary electrical characteristics freescale semiconductor 32 figure 13. sram read bus cycle terminated by tea figure 14 shows an sdram read cycle. clkout cs n a[23:0] oe r/w bs [3:0] tea (h) s0 s2 s3 s1 s4 s5 s0 s1 ta (h) b6a b8 b7a b9 b6c b7 b6b b7 b2a b1a d[31:0] b8 b9 ts b9 tip b8 tsiz[ 1:0]
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 33 figure 14. sdram read cycle figure 15 shows an sdram write cycle. table 13. sdram timing num characteristic symbol min max unit d1 clkout high to sdram address valid t chdav ?9ns d2 clkout high to sdram control valid t chdcv ?9ns d3 clkout high to sdram address invalid t chdai 1.5 ? ns d4 clkout high to sdram control invalid t chdci 1.5 ? ns d5 sdram data valid to clkout high t ddvch 4?ns d6 clkout high to sdram data invalid t chddi 1.5 ? ns d7 1 1 d7 and d8 are for write cycles only. clkout high to sdram data valid t chddvw ?9ns d8 2 clkout high to sdram data invalid t chddiw 1.5 ? ns a[23:0] sd_sras d[31:0] actv nop pall nop ras [1:0] read column sd_cke 0 sdwe cas [3:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d1 d2 d4 d6 d5 d4 d4 1 dacr[casl] = 2 sd_cas 1 nop d4 row d3 d2 d2 d2 d2
mcf523x integrated microprocessor hardware specification, rev. 2 preliminary electrical characteristics freescale semiconductor 34 figure 15. sdram write cycle 7.7 general purpose i/o timing table 14. gpio timing 1 1 gpio pins include: int, etpu, uart, flexcan and timer pins. num characteristic symbol min max unit g1 g2 clkout high to gpio output valid t chpov ?10ns clkout high to gpio output invalid t chpoi 1.5 ? ns g3 g4 gpio input valid to clkout high t pvch 9?ns clkout high to gpio input invalid t chpi 1.5 ? ns a[23:0] sd_sras sd_scas 1 d[31:0] actv pall nop ras [1:0] write row column sd_cke sd_we cas [3:0] d1 d2 d4 d8 0 1 2 3 4 5 6 7 8 9 10 11 12 d7 nop 1 dacr[casl] = 2 d4 d3 d2 d2 d2 d4 d2
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 35 figure 16. gpio timing 7.8 reset and configuration override timing figure 17. reset and configuration override timing refer to the chip configuration module (ccm) chapter in the device?s reference manual for more information. table 15. reset and configuration override timing (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) 1 1 all ac timing is shown with respect to 50% v dd levels unless otherwise noted. num characteristic symbol min max unit r1 reset input valid to clkout high t rvch 9?ns r2 clkout high to reset input invalid t chri 1.5 ? ns r3 reset input valid time 2 2 during low power stop, the synchronizers for the reset input are bypassed and reset is asserted asynchronously to the system. thus, reset must be held a minimum of 100 ns. t rivt 5?t cyc r4 clkout high to rstout valid t chrov ?10ns r5 rstout valid to config. overrides valid t rovcv 0?ns r6 configuration override setup time to rstout invalid t cos 20 ? t cyc r7 configuration override hold time after rstout invalid t coh 0?ns r8 rstout invalid to configuration override high impedance t roicz ?1t cyc g2 g1 g4 g3 clkout gpio outputs gpio inputs r1 r2 clkout reset rstout r3 r4 r8 r7 r6 r5 configuration overrides*: r4 (rcon , override pins])
mcf523x integrated microprocessor hardware specification, rev. 2 preliminary electrical characteristics freescale semiconductor 36 7.9 i 2 c input/output timing specifications table 16 lists specifications for the i 2 c input timing parameters shown in figure 18 . table 17 lists specifications for the i 2 c output timing parameters shown in figure 18 . figure 18 shows timing for the values in table 16 and table 17 . table 16. i 2 c input timing specifications between i2c_scl and i2c_sda num characteristic min max units i1 start condition hold time 2 ? t cyc i2 clock low period 8 ? t cyc i3 i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 1 ms i6 clock high time 4 ? t cyc i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 ? t cyc i9 stop condition setup time 2 ? t cyc table 17. i 2 c output timing specifications between i2c_scl and i2c_sda num characteristic min max units i1 1 1 note: output numbers depend on the value progra mmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta b l e 1 7 . the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the i2c_scl low period. the actual position is affect ed by the prescale and division values programmed into the ifdr; however, the numbers given in ta bl e 1 7 are minimum values. start condition hold time 6 ? t cyc i2 1 clock low period 10 ? t cyc i3 2 2 because i2c_scl and i2c_sda are open-collector-t ype outputs, which the processor can only actively drive low, the time i2c_scl or i2c_sda take to reach a high level depends on external signal capacitance and pull-up resistor values. i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ? ? s i4 1 data hold time 7 ? t cyc i5 3 3 specified at a nominal 50-pf load. i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 3 ns i6 1 clock high time 10 ? t cyc i7 1 data setup time 2 ? t cyc i8 1 start condition setup time (for repeated start condition only) 20 ? t cyc i9 1 stop condition setup time 10 ? t cyc
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 37 figure 18. i 2 c input/output timings 7.10 fast ethernet ac timing specifications mii signals use ttl signal levels compatible with devices operating at either 5.0 v or 3.3 v. 7.10.1 mii receive signal timing (erxd[3:0], erxdv, erxer, and erxclk) the receiver functions co rrectly up to a erxclk maximum fre quency of 25 mhz +1%. the processor clock frequency must exceed twice the erxclk frequency. table 18 lists mii receive channel timings. figure 19 shows mii receive sign al timings listed in table 18 . figure 19. mii receive signal timing diagram table 18. mii receive signal timing num characteristic min max unit m1 erxd[3:0], erxdv, erxer to erxclk setup 5 ? ns m2 erxclk to erxd[3:0], erxdv, erxer hold 5 ? ns m3 erxclk pulse width high 35% 65% erxclk period m4 erxclk pulse width low 35% 65% erxclk period i2 i6 i1 i4 i7 i8 i9 i5 i3 i2c_scl i2c_sda m1 m2 erxclk (input) erxd[3:0] (inputs) erxdv erxer m3 m4
mcf523x integrated microprocessor hardware specification, rev. 2 preliminary electrical characteristics freescale semiconductor 38 7.10.2 mii transmit signal timing (e txd[3:0], etxen, etxer, etxclk) table 19 lists mii transmit channel timings. the transmitter functions correct ly up to a etxclk maximum freque ncy of 25 mhz +1%. the processor clock frequency must exceed twice the etxclk frequency. figure 20 shows mii transmit si gnal timings listed in table 19 . figure 20. mii transmit signal timing diagram 7.10.3 mii async inputs signal timing (ecrs and ecol) table 20 lists mii asynchronous inputs signal timing. figure 21 shows mii asynchronous i nput timings listed in table 20 . figure 21. mii async inputs timing diagram table 19. mii transmit signal timing num characteristic min max unit m5 etxclk to etxd[3:0], etxen, etxer invalid 5 ? ns m6 etxclk to etxd[3:0], etxen, etxer valid ? 25 ns m7 etxclk pulse width high 35% 65% etxclk period m8 etxclk pulse width low 35% 65% etxclk period table 20. mii async inputs signal timing num characteristic min max unit m9 ecrs, ecol minimum pulse width 1.5 ? etxclk period m6 etxclk (input) etxd[3:0] (outputs) etxen etxer m5 m7 m8 ecrs, ecol m9
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 39 7.10.4 mii serial management channel timing (emdio and emdc) table 21 lists mii serial management channel timings. the fec functio ns correctly with a maximum mdc frequency of 2.5 mhz. figure 22 shows mii serial management channel timings listed in table 21 . figure 22. mii serial management channel timing diagram 7.11 32-bit timer module ac timing specifications table 22 lists timer module ac timings. table 21. mii serial management channel timing num characteristic min max unit m10 emdc falling edge to emdio output invalid (minimum propagation delay) 0 ? ns m11 emdc falling edge to emdio output valid (max prop delay) ? 25 ns m12 emdio (input) to emdc rising edge setup 10 ? ns m13 emdio (input) to emdc rising edge hold 0 ? ns m14 emdc pulse width high 40% 60% mdc period m15 emdc pulse width low 40% 60% mdc period emdc (output) emdio (output) m12 m13 emdio (input) m10 m14 m15 m11
mcf523x integrated microprocessor hardware specification, rev. 2 preliminary electrical characteristics freescale semiconductor 40 7.12 qspi electrical specifications table 23 lists qspi timings. the values in table 23 correspond to figure 23 . figure 23. qspi timing table 22. timer module ac timing specifications name characteristic 0?66 mhz unit min max t1 dt0in / dt1in / dt2in / dt3in cycle time 3 ? t cyc t2 dt0in / dt1in / dt2in / dt3in pulse width 1 ? t cyc table 23. qspi modules ac timing specifications name characteristic min max unit qs1 qspi_cs[1:0] to qspi_clk 1 510 tcyc qs2 qspi_clk high to qspi_dout valid. ? 10 ns qs3 qspi_clk high to qspi_dout invalid. (output hold) 2 ? ns qs4 qspi_din to qspi_clk (input setup) 9 ? ns qs5 qspi_din to qspi_clk (input hold) 9 ? ns qspi_cs[1:0] qspi_clk qspi_dout qs5 qs1 qspi_din qs3 qs4 qs2
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 41 7.13 jtag and boundary scan timing figure 24. test clock input timing table 24. jtag and boundary scan timing num characteristics 1 1 jtag_en is expected to be a static signal. hence, specific timing is not associated with it. symbol min max unit j1 tclk frequency of operation f jcyc dc 1/4 f sys/2 j2 tclk cycle period t jcyc 4?t cyc j3 tclk clock pulse width t jcw 26 ? ns j4 tclk rise and fall times t jcrf 03ns j5 boundary scan input data setup time to tclk rise t bsdst 4?ns j6 boundary scan input data hold time after tclk rise t bsdht 26 ? ns j7 tclk low to boundary scan output data valid t bsdv 033ns j8 tclk low to boundary scan output high z t bsdz 033ns j9 tms, tdi input data se tup time to tclk rise t tapbst 4?ns j10 tms, tdi input data hold time after tclk rise t tapbht 10 ? ns j11 tclk low to tdo data valid t tdodv 026ns j12 tclk low to tdo high z t tdodz 08ns j13 trst assert time t trstat 100 ? ns j14 trst setup time (negation) to tclk high t trstst 10 ? ns tclk v il v ih j3 j3 j4 j4 j2 (input)
mcf523x integrated microprocessor hardware specification, rev. 2 preliminary electrical characteristics freescale semiconductor 42 figure 25. boundary scan (jtag) timing figure 26. test access port timing figure 27. trst timing 7.14 debug ac timing specifications table 25 lists specifications for the de bug ac timing parameters shown in figure 29 . input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j5 j6 j7 j8 j7 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst j14 j13
preliminary electrica l characteristics mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 43 figure 28 shows real-time trace timing for the values in table 25 . figure 28. real-time trace ac timing figure 29 shows bdm serial port ac timing for the values in table 25 . table 25. debug ac timing specification num characteristic 150 mhz units min max de0 pstclk cycle time ? 0.5 t cyc de1 pst valid to pstclk high 4 ? ns de2 pstclk high to pst invalid 1.5 ? ns de3 dsclk cycle time 5 ? t cyc de4 dsi valid to dsclk high 1 ? t cyc de5 1 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of clkout. dsclk high to dso invalid 4 ? t cyc de6 bkpt input data setup time to clkout rise 4 ? ns de7 clkout high to bkpt high z 0 10 ns pstclk pst[3:0] de2 de1 ddata[3:0] de0
mcf523x integrated microprocessor hardware specification, rev. 2 documentation freescale semiconductor 44 figure 29. bdm serial port ac timing 8 documentation documentation regarding the mcf523 x and their development support t ools is available from a local freescale distributor, a fr eescale semiconductor sa les office, the freescale lite rature distribution center, or through the freescal e web address at http://www.freescale.com /coldfire . 9 document revision history the below table provides a revi sion history for this document. table 26. document revision history rev. no. substantive change(s) 0 preliminary release. 1 updated signal list table 1.1 removed duplicate information in the module de scription sections. the information is all in the signals description table. 1.2 corrected figure 8 pin 81. vdd instead of vss changed instances of motorola to freescale 1.3 removed detailed signal description sectio n. this information can be found in the mcf5235rm chapter 2. removed detailed feature list. this information can be found in the mcf5235rm chapter 1. corrected figure 2 pin f10. vss instead of vdd. change made in ta b l e 2 as well. corrected figure 8 pin 81. ovdd instead of vdd. change made in ta b l e 2 as well. cleaned up many inconsistencies within the pinout figure signal names corrected document ids in documentation table 1.4 added values for ?maximum operating junction temperature? in ta b l e 8 . added typical values for ?core operat ing supply current (master mode)? in ta bl e 9 . added typical values for ?pad operating supply current (master mode)? in ta bl e 9 . removed unnecessary pll specifications, #6-9, in ta b l e 1 0 . dsi dso current next clkout past current dsclk de3 de4 de5 bkpt de6 de7
document revision history mcf523x integrated microprocessor hardware specification, rev. 2 freescale semiconductor 45 1.5 removed overview, features, modes of operat ion, and address multiplexing sections. this information can be found in the mcf5235 reference manual. removed list of documentation table in section 8, ?documentation .? . an up-to-date list is always available on our web site. 1.6 ta bl e 9 : changed core supply voltage (v dd ) from 1.35-1.65 to 1.4-1.6. 1.7 ta bl e 1 0 : changed max f ico frequency from ?75 mhz? to ?150 mhz?. 1.8 added section 5.2.1, ?supply voltage sequencing and separation cautions .? updated 196mapbga package dimensions, figure 3 . 2 ta bl e 2 : changed sd_cke pin location from 139 to ??? for the 160qfp device. changed qspi_cs1 pin location from ??? to 139 for the 160qfp device. figure 8 : changed pin 139 label from ?sd_cke/qspi_cs1? to ?qspi_cs1/sd_cke?. removed second sentence from section 7.10.1, ?mii receive signal timing (erxd[3:0], erxdv, erxer, and erxclk) ,? and section 7.10.2, ?mii transmit signal timing (etxd[3:0], etxen, etxer, etxclk) ,? regarding no minimum frequency requirement for txclk. removed third and fourth paragraphs from section 7.10.2, ?mii tr ansmit signal timing (etxd[3:0], etxen, etxer, etxclk) ,? as this feature is not supported on this device. table 26. document revision history (continued) rev. no. substantive change(s)
document number: mcf5235ec rev. 2 08/2006 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2006. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp .

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